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june 1998 ML4824 * power factor correction and pwm controller combo 1 general description the ML4824 is a controller for power factor corrected, switched mode power supplies. power factor correction (pfc) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching fets, and results in a power supply that fully complies with iec1000-2-3 specification. the ML4824 includes circuits for the implementation of a leading edge, average current, boost type power factor correction and a trailing edge, pulse width modulator (pwm). the device is available in two versions; the ML4824-1 (f pwm = f pfc ) and the ML4824-2 (f pwm = 2 x f pfc ). doubling the switching frequency of the pwm allows the user to design with smaller output components while maintaining the best operating frequency for the pfc. an over-voltage comparator shuts down the pfc section in the event of a sudden decrease in load. the pfc section also includes peak current limiting and input voltage brown- out protection. the pwm section can be operated in current or voltage mode at up to 250khz and includes a duty c ycle limit to pre v ent t r ansformer saturation. fe a tures n internally synchronized pfc and pwm in one ic n low total harmonic distortion n reduces ripple current in the storage capacitor between the pfc and pwm sections n average current, continuous boost leading edge pfc n fast transconductance error amp for voltage loop n high efficiency trailing edge pwm can be configured for current mode or voltage mode operation n average line voltage compensation with brownout control n pfc overvoltage comparator eliminates output runaway due to load removal n current fed gain modulator for impr o v ed noise immunity n over v oltage protection, uvl o , and soft start 15 veao ieao v fb i ac v rms i sense ramp 1 oscillator ovp pfc i limit uvlo v ref pulse width modulator power factor corrector 2.5v + C C + 16 2 4 3 7.5v reference 14 v cc 13 v ccz vea 7 + C iea 1 + C + C pfc out 12 s r q q s r q q 2.7v C1v ramp 2 8 pwm out 11 s r q q v dc 6 ss 5 dc i limit 9 v cc duty cycle limit C + 1v C + 2.5v v fb C + 8v 8v v in ok gain modulator v ccz x 2 (-2 version only) 3.5k w 3.5k w 1.25v 50a C + 13.5v dc i limit block di a gram * so me pa cka ges a re o bso l e t e
ML4824 2 pin configuration pin description pin name function 9 dc i limit pwm current limit comparator input 10 gnd ground 11 pwm out pwm driver output 12 pfc out pfc driver output 13 v cc positive supply (connected to an internal shunt regulator) 14 v ref buffered output for the internal 7.5v reference 15 v fb pfc transconductance voltage error amplifier input 16 veao pfc transconductance voltage error amplifier output pin name function 1 ieao pfc transconductance current error amplifier output 2i ac pfc gain control reference input 3i sense current sense input to the pfc current limit comparator 4v rms input for pfc rms line voltage compensation 5 ss connection point for the pwm soft start capacitor 6v dc pwm voltage feedback input 7 ramp 1 oscillator timing node; timing set by r t c t 8 ramp 2 when in current mode, this pin functions as as the current sense input; when in voltage mode, it is the pwm input from pfc output (feed forward ramp). 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ieao i ac i sense v rms ss v dc ramp 1 ramp 2 veao v fb v ref v cc pfc out pwm out gnd dc i limit top view ML4824 16-pin pdip (p16) 16-pin wide soic (s16w)
ML4824 3 absolute maximum ratings absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device operation is not implied. v cc shunt regulator current .................................. 55ma i sense voltage ..................................................C3v to 5v voltage on any other pin ... gnd C 0.3v to v ccz + 0.3v i ref ............................................................................................ 20ma i ac input current .................................................... 10ma peak pfc out current, source or sink ................ 500ma peak pwm out current, source or sink .............. 500ma pfc out, pwm out energy per cycle .................. 1.5j junction temperature .............................................. 150c storage temperature range ..................... C65c to 150c lead temperature (soldering, 10 sec) ..................... 260c thermal resistance ( q ja ) plastic dip ....................................................... 80c/w plastic soic ................................................... 105c/w operating conditions temperature range ML4824cx ................................................. 0c to 70c ML4824ix .............................................. C40c to 85c electrical characteristics unless otherwise specified, i cc = 25ma, r t = 52.3k w , c t = 470pf, t a = operating temperature range (note 1) symbol parameter conditions min typ max units voltage error amplifier input voltage range 0 7 v transconductance v non inv = v inv , veao = 3.75v 50 85 120 feedback reference voltage 2.46 2.53 2.60 v input bias current note 2 -0.3 C1.0 a output high voltage 6.0 6.7 v output low voltage 0.6 1.0 v source current d v in = 0.5v, v out = 6v C40 C80 a sink current d v in = 0.5v, v out = 1.5v 40 80 a open loop gain 60 75 db power supply rejection ratio v ccz - 3v < v cc < v ccz - 0.5v 60 75 db current error amplifier input voltage range C1.5 2 v transconductance v non inv = v inv , veao = 3.75v 130 195 310 input offset voltage 0 8 15 mv input bias current C0.5 C1.0 a output high voltage 6.0 6.7 v output low voltage 0.6 1.0 v source current d v in = 0.5v, v out = 6v C40 C90 a sink current d v in = 0.5v, v out = 1.5v 40 90 a open loop gain 60 75 db power supply rejection ratio v ccz - 3v < v cc < v ccz - 0.5v 60 75 db w w
ML4824 4 electrical characteristics (continued) smbol parameter conditions min typ max units ovp comparator threshold voltage 2.6 2.7 2.8 v hysteresis 80 115 150 mv pfc i limit comparator threshold voltage C0.8 C1.0 C1.15 v d (pfc i limit v th - gain modulator output) 100 190 mv delay to output 150 300 ns dc i limit comparator threshold voltage 0.97 1.02 1.07 v input bias current 0.3 1 a delay to output 150 300 ns v in ok comparator threshold voltage 2.4 2.5 2.6 v hysteresis 0.8 1.0 1.2 v gain modulator gain (note 3) i ac = 100a, v rms = v fb = 0v 0.36 0.55 0.66 i ac = 50a, v rms = 1.2v, v fb = 0v 1.20 1.80 2.24 i ac = 50a, v rms = 1.8v, v fb = 0v 0.55 0.80 1.01 i ac = 100a, v rms = 3.3v, v fb = 0v 0.14 0.20 0.26 bandwidth iac = 100a 10 mhz output voltage i ac = 250a, v rms = 1.15v, 0.74 0.82 0.90 v v fb = 0v oscillator initial accuracy t a = 25c 71 76 81 khz voltage stability v ccz - 3v < v cc < v ccz - 0.5v 1 % temperature stability 2% total variation line, temp 68 84 khz ramp valley to peak voltage 2.5 v dead time pfc only 270 370 470 ns c t discharge current v ramp 2 = 0v, v ramp 1 = 2.5v 4.5 7.5 9.5 ma reference output voltage t a = 25c, i(v ref ) = 1ma 7.4 7.5 7.6 v line regulation v ccz - 3v < v cc < v ccz - 0.5v 2 10 mv load regulation 1ma < i(v ref ) < 20ma 2 15 mv temperature stability 0.4 % total variation line, load, temp 7.35 7.65 v long term stability t j = 125c, 1000 hours 5 25 mv
ML4824 5 electrical characteristics (continued) symbol parameter conditions min typ max units pfc minimum duty cycle v ieao > 4.0v 0 % maximum duty cycle v ieao < 1.2v 90 95 % output low voltage i out = -20ma 0.4 0.8 v i out = -100ma 0.8 2.0 v i out = 10ma, v cc = 8v 0.7 1.5 v output high voltage i out = 20ma 10 10.5 v i out = 100ma 9.5 10 v rise/fall time c l = 1000pf 50 ns pwm duty cycle range ML4824-1 0-44 0-47 0-50 % ML4824-2 0-37 0-40 0-45 % output low voltage i out = -20ma 0.4 0.8 v i out = -100ma 0.8 2.0 v i out = 10ma, v cc = 8v 0.7 1.5 v output high voltage i out = 20ma 10 10.5 v i out = 100ma 9.5 10 v rise/fall time c l = 1000pf 50 ns supply shunt regulator voltage (v ccz ) 12.8 13.5 14.2 v v ccz load regulation 25ma < i cc < 55ma 100 300 mv v ccz total variation load, temp 12.4 14.6 v start-up current v cc = 11.8v, c l = 0 0.7 1.0 ma operating current v cc < v ccz - 0.5v, c l = 0 16 19 ma undervoltage lockout threshold 12 13 14 v undervoltage lockout hysteresis 2.7 3.0 3.3 v note 1: limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. note 2: includes all bias currents to other circuits connected to the v fb pin. note 3: gain = k x 5.3v; k = (i gainmod - i offset ) x i ac x (veao - 1.5v) -1 .
ML4824 6 typical performance characteristics 250 200 150 100 50 0 transconductance ( ) v fb (v) 05 3 w 14 2 250 200 150 100 50 0 transconductance ( ) iea input voltage (mv) C500 500 0 w 400 300 200 100 0 variable gain block constant - k v rms (mv) 05 3 14 2 voltage error amplifier (vea) transconductance (g m ) current error amplifier (iea) transconductance (g m ) gain modulator transfer characteristic (k) 15 veao ieao v fb i ac v rms i sense ramp 1 oscillator ovp pfc i limit 2.5v + C C + 16 2 4 3 vea 7 + C iea 1 + C + C pfc out 12 s r q q s r q q 2.7v C1v 3.5k w 3.5k w gain modulator figure 1. pfc section block diagram.
ML4824 7 functional description the ML4824 consists of an average current controlled, continuous boost power factor corrector (pfc) front end and a synchronized pulse width modulator (pwm) back end. the pwm can be used in either current or voltage mode. in voltage mode, feedforward from the pfc output buss can be used to improve the pwms line regulation. in either mode, the pwm stage uses conventional trailing- edge duty cycle modulation, while the pfc uses leading- edge modulation. this patented leading/trailing edge modulation technique results in a higher useable pfc error amplifier bandwidth, and can significantly reduce the size of the pfc dc buss capacitor. the synchronization of the pwm with the pfc simplifies the pwm compensation due to the controlled ripple on the pfc output capacitor (the pwm input capacitor). the pwm section of the ML4824-1 runs at the same frequency as the pfc. the pwm section of the ML4824-2 runs at twice the frequency of the pfc, which allows the use of smaller pwm output magnetics and filter capacitors while holding down the losses in the pfc stage power components. in addition to power factor correction, a number of protection features have been built into the ML4824. these include soft-start, pfc over-voltage protection, peak current limiting, brown-out protection, duty cycle limit, and under-voltage lockout. power factor correction power factor correction makes a non-linear load look like a resistive load to the ac line. for a resistor, the current drawn from the line is in phase with and proportional to the line voltage, so the power factor is unity (one). a common class of non-linear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. the peak-charging effect which occurs on the input filter capacitor in these supplies causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. such supplies present a power factor to the line of less than one (i.e. they cause significant current harmonics of the power line frequency to appear at their input). if the input current drawn by such a supply (or any other non-linear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the ac line and a unity power factor will be achieved. to hold the input current draw of a device drawing power from the ac line in phase with and proportional to the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. the pfc section of the ML4824 uses a boost-mode dc-dc converter to accomplish this. the input to the converter is the full wave rectified ac line voltage. no bulk filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges (at twice line frequency) from zero volts to the peak value of the ac input and back to zero. by forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current which the converter draws from the power line agrees with the instantaneous line voltage. one of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. a commonly used value is 385vdc, to allow for a high line of 270vac rms . the other condition is that the current which the converter is allowed to draw from the line at any given instant must be proportional to the line voltage. the first of these requirements is satisfied by establishing a suitable voltage control loop for the converter, which in turn drives a current error amplifier and switching output driver. the second requirement is met by using the rectified ac line voltage to modulate the output of the voltage control loop. such modulation causes the current error amplifier to command a power stage current which varies directly with the input voltage. in order to prevent ripple which will necessarily appear at the output of the boost circuit (typically about 10vac on a 385v dc level) from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. a final refinement is to adjust the overall gain of the pfc such to be proportional to 1/v in 2 , which linearizes the transfer function of the system as the ac input voltage varies. since the boost converter topology in the ML4824 pfc is of the current-averaging type, no slope compensation is required. pfc section gain modulator figure 1 shows a block diagram of the pfc section of the ML4824. the gain modulator is the heart of the pfc, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line voltage, and pfc output voltage. there are three inputs to the gain modulator. these are: 1) a current representing the instantaneous input voltage (amplitude and waveshape) to the pfc. the rectified ac input sine wave is converted to a proportional current via a resistor and is then fed into the gain modulator at i ac . sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. the gain modulator responds linearly to this current. 2) a voltage proportional to the long-term rms ac line voltage, derived from the rectified line voltage after scaling and filtering. this signal is presented to the gain modulator at v rms . the gain modulators output is inversely proportional to v rms 2 (except at unusually low values of v rms where special gain contouring takes over, to limit power dissipation of the circuit components under heavy brownout conditions). the relationship between v rms and gain is called k, and is illustrated in the typical performance characteristics.
ML4824 8 3) the output of the voltage error amplifier, veao. the gain modulator responds linearly to variations in this voltage. the output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. this current is applied to the virtual-ground (negative) input of the current error amplifier. in this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the pfc from the power line. the general form for the output of the gain modulator is: i iveao v v gainmod ac rms = 2 1 (1) more exactly, the output current of the gain modulator is given by: i k veao v i gainmod ac = - (.) 15 where k is in units of v -1 . note that the output current of the gain modulator is limited to @ 200a. current error amplifier the current error amplifiers output controls the pfc duty cycle to keep the average current through the boost inductor a linear function of the line voltage. at the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the i sense pin (current into i sense @ v sense /3.5k w ). the negative voltage on i sense represents the sum of all currents flowing in the pfc circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. in higher power applications, two current transformers are sometimes used, one to monitor the i d of the boost mosfet(s) and one to monitor the i f of the boost diode. as stated above, the inverting input of the current error amplifier is a virtual ground. given this fact, and the arrangement of the duty cycle modulator polarities internal to the pfc, an increase in positive current from the gain modulator will cause the output stage to increase its duty cycle until the voltage on i sense is adequately negative to cancel this increased current. similarly, if the gain modulators output decreases, the output duty cycle will decrease, to achieve a less negative voltage on the i sense pin. cycle-by-cycle current limiter the i sense pin, as well as being a part of the current feedback loop, is a direct input to the cycle-by-cycle current limiter for the pfc section. should the input voltage at this pin ever be more negative than -1v, the output of the pfc will be disabled until the protection flip- flop is reset by the clock pulse at the start of the next pfc power cycle. functional description (continued) figure 2. compensation network connections for the voltage and current error amplifiers 15 veao ieao v fb i ac v rms i sense 2.5v C + 16 2 4 3 vea + C iea + C v ref 1 pfc output gain modulator overvoltage protection the ovp comparator serves to protect the power circuit from being subjected to excessive voltages if the load should suddenly change. a resistor divider from the high voltage dc output of the pfc is fed to v fb . when the voltage on v fb exceeds 2.7v, the pfc output driver is shut down. the pwm section will continue to operate. the ovp comparator has 125mv of hysteresis, and the pfc will not restart until the voltage at v fb drops below 2.58v. the v fb should be set at a level where the active and passive external power components and the ML4824 are within their safe operating voltages, but not so low as to interfere with the boost voltage regulation loop. error amplifier compensation the pwm loading of the pfc can be modeled as a negative resistor; an increase in input voltage to the pwm causes a decrease in the input current. this response dictates the proper compensation of the two transconductance error amplifiers. figure 2 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. the current loop compensation is returned to v ref to produce a soft-start characteristic on the pfc: as the reference voltage comes up from zero volts, it creates a differentiated voltage on ieao which prevents the pfc from immediately demanding a full duty cycle on its boost converter. there are two major concerns when compensating the voltage loop error amplifier; stability and transient response. optimizing interaction between transient response and stability requires that the error amplifiers
ML4824 9 functional description (continued) open-loop crossover frequency should be 1/2 that of the line frequency, or 23hz for a 47hz line (lowest anticipated international power frequency). the gain vs. input voltage of the ML4824s voltage error amplifier has a specially shaped nonlinearity such that under steady-state operating conditions the transconductance of the error amplifier is at a local minimum. rapid perturbations in line or load conditions will cause the input to the voltage error amplifier (v fb ) to deviate from its 2.5v (nominal) value. if this happens, the transconductance of the voltage error amplifier will increase significantly, as shown in the typical performance characteristics. this raises the gain- bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with a conventional linear gain characteristic. the current amplifier compensation is similar to that of the voltage error amplifier with the exception of the choice of crossover frequency. the crossover frequency of the current amplifier should be at least 10 times that of the voltage amplifier, to prevent interaction with the voltage loop. it should also be limited to less than 1/6th that of the switching frequency, e.g. 16.7khz for a 100khz switching frequency. there is a modest degree of gain contouring applied to the transfer characteristic of the current error amplifier, to increase its speed of response to current-loop perturbations. however, the boost inductor will usually be the dominant factor in overall current loop response. therefore, this contouring is significantly less marked than that of the voltage error amplifier. this is illustrated in the typical performance characteristics. for more information on compensating the current and voltage control loops, see application notes 33 and 34. application note 16 also contains valuable information for the design of this class of pfc. oscillator (ramp 1) the oscillator frequency is determined by the values of r t and c t , which determine the ramp and off-time of the oscillator output clock: f tt osc ramp deadtime = + 1 (2) the deadtime of the oscillator is derived from the following equation: tcrin v v ramp t t ref ref = - - f h g i k j 125 375 . . (3) at v ref = 7.5v: tcr ramp t t = 051 . the deadtime of the oscillator may be determined using: t v ma cc deadtime t t == 25 51 490 . . (4) the deadtime is so small (t ramp >> t deadtime ) that the operating frequency can typically be approximated by: f t osc ramp = 1 (5) example: for the application circuit shown in the data sheet, with the oscillator running at: fkhz t osc ramp == 100 1 tcr ramp t t = = - 051110 5 . solving for r t x c t yields 2 x 10 -4 . selecting standard components values, c t = 470pf, and r t = 41.2k w . the deadtime of the oscillator adds to the maximum pwm duty cycle (it is an input to the duty cycle limiter). with zero oscillator deadtime, the maximum pwm duty cycle is typically 45%. in many applications, care should be taken that c t not be made so large as to extend the maximum duty cycle beyond 50%. this can be accomplished by using a stable 470pf capacitor for c t . pwm section pulse width modulator the pwm section of the ML4824 is straightforward, but there are several points which should be noted. foremost among these is its inherent synchronization to the pfc section of the device, from which it also derives its basic timing (at the pfc frequency in the ML4824-1, and at twice the pfc frequency in the ML4824-2). the pwm is capable of current-mode or voltage mode operation. in current-mode applications, the pwm ramp (ramp 2) is usually derived directly from a current sensing resistor or current transformer in the primary of the output stage, and is thereby representative of the current flowing in the converters output stage. dc i limit , which provides cycle- by-cycle current limiting, is typically connected to ramp 2 in such applications. for voltage-mode operation or certain specialized applications, ramp 2 can be connected to a separate rc timing network to generate a voltage ramp against which v dc will be compared. under these conditions, the use of voltage feedforward from the pfc buss can assist in line regulation accuracy and response. as in current mode operation, the dc i limit input is used for output stage overcurrent protection.
ML4824 10 functional description (continued) figure 3. external component connections to v cc no voltage error amplifier is included in the pwm stage of the ML4824, as this function is generally performed on the output side of the pwms isolation boundary. to facilitate the design of optocoupler feedback circuitry, an offset has been built into the pwms ramp 2 input which allows v dc to command a zero percent duty cycle for input voltages below 1.25v. pwm current limit the dc i limit pin is a direct input to the cycle-by-cycle current limiter for the pwm section. should the input voltage at this pin ever exceed 1v, the output of the pwm will be disabled until the output flip-flop is reset by the clock pulse at the start of the next pwm power cycle. v in ok comparator the v in ok comparator monitors the dc output of the pfc and inhibits the pwm if this voltage on v fb is less than its nominal 2.5v. once this voltage reaches 2.5v, which corresponds to the pfc output capacitor being charged to its rated boost voltage, the soft-start begins. pwm control (ramp 2) when the pwm section is used in current mode, ramp 2 is generally used as the sampling point for a voltage representing the current in the primary of the pwms output transformer, derived either by a current sensing resistor or a current transformer. in voltage mode, it is the input for a ramp voltage generated by a second set of timing components (r ramp2 , c ramp2 ), which will have a minimum value of zero volts and should have a peak value of approximately 5v. in voltage mode operation, feedforward from the pfc output buss is an excellent way to derive the timing ramp for the pwm stage. soft start start-up of the pwm is controlled by the selection of the external capacitor at ss. a current source of 50a supplies the charging current for the capacitor, and start-up of the pwm begins at 1.25v. start-up delay can be programmed by the following equation: ct a v ss delay = 50 125 m . (6) where c ss is the required soft start capacitance, and t delay is the desired start-up delay. it is important that the time constant of the pwm soft-start allow the pfc time to generate sufficient output power for the pwm section. the pwm start-up delay should be at least 5ms. solving for the minimum value of c ss : cms a v nf ss = = 5 50 125 200 m . generating v cc the ML4824 is a current-fed part. it has an internal shunt voltage regulator, which is designed to regulate the voltage internal to the part at 13.5v. this allows a low power dissipation while at the same time delivering 10v of gate drive at the pwm out and pfc out outputs. it is important to limit the current through the part to avoid overheating or destroying it. this can be easily done with a single resistor in series with the vcc pin, returned to a bias supply of typically 18v to 20v. the resistors value must be chosen to meet the operating current requirement of the ML4824 itself (19ma max) plus the current required by the two gate driver outputs. example: with a v bias of 20v, a v cc limit of 14.6v (max) and the ML4824 driving a total gate charge of 110nc at 100khz (e.g., 1 irf840 mosfet and 2 irf830 mosfets), the gate driver current required is: ikhzncma gatedrive == 100 100 11 (7) r vv ma ma bias = - + = 20 146 19 11 180 . w (8) to check the maximum dissipation in the ML4824, find the current at the minimum v cc (12.4v): i vv ma cc = - = 20 12 4 180 42 2 . . w (9) the maximum allowable i cc is 55ma, so this is an acceptable design. the ML4824 should be locally bypassed with a 10nf and a 1 m f ceramic capacitor. in most applications, an electrolytic capacitor of between 100 m f and 330 m f is also required across the part, both for filtering and as part of the start-up bootstrap circuitry. ML4824 v cc gnd v bias 10nf ceramic 1f ceramic r bias
ML4824 11 leading/trailing modulation conventional pulse width modulation (pwm) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. the error amplifier output voltage is then compared with the modulating ramp. when the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned off. when the switch is on, the inductor current will ramp up. the effective duty cycle of the trailing edge modulation is determined during the on time of the switch. figure 4 shows a typical trailing edge control scheme. in the case of leading edge modulation, the switch is turned off right at the leading edge of the system clock. when the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned on. the effective duty-cycle of the leading edge modulation is determined during the off time of the switch. figure 5 shows a leading edge control scheme. one of the advantages of this control teccnique is that it requires only one system clock. switch 1 (sw1) turns off and switch 2 (sw2) turns on at the same instant to minimize the momentary no-load period, thus lowering ripple voltage generated by the switching action. with such synchronized switching, the ripple voltage of the first stage is reduced. calculation and evaluation have shown that the 120hz component of the pfcs output ripple voltage can be reduced by as much as 30% using this method. typical applications figure 6 is the application circuit for a complete 100w power factor corrected power supply, designed using the methods and general topology detailed in application note 33. figure 4. typical trailing edge control scheme. ramp veao time vsw1 time ref ea C + C + osc dff r d q q clk u1 ramp clk u4 u3 c1 rl i4 sw2 sw1 + dc i1 i2 i3 vin l1 u2
ML4824 12 figure 5. typical leading edge control scheme. ref ea C + C + osc dff r d q q clk u1 ramp clk u4 u3 c1 rl i4 sw2 sw1 + dc i1 i2 i3 vin l1 veao cmp u2 ramp veao time vsw1 time
ML4824 13 figure 6. 100w power factor corrected power supply, designed using micro linear application note 33. ac input 85 to 265vac c1 470nf ML4824 f1 3.15a r5 300m w 1w br1 4a, 600v d12 1a, 50v d13 1a, 50v r2a 357k w r2b 357k w r3 75k w r4 13k w r1a 499k w r1b 499k w r12 27k w c6 1nf c7 220pf r11 750k w c19 1f c2 470nf r27 39k w c18 470pf r6 41.2k w r10 6.2k w c11 10nf c3 470nf c30 330f r21 22 w c4 10nf d1 8a, 600v c5 100f r14 33 w d10 1a, 20v d8 1a, 20v r7a 178k w r7b 178k w c12 10f d3 50v q1 irf840 q2 irf830 c13 100nf c14 1f ieao i ac i sense v rms ss v dc ramp 1 ramp 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 veao v fb v ref v cc pfc out pwm out gnd dc i limit q3 irf830 r15 3 w c20 1f r28 180 w 12vdc l1 3.1mh l2 33h c21 1800f c24 1f rtn d11 mbr2545ct d5 600v d6 600v c25 100nf r17 33 w r30 4.7k w d7 15v r22 8.66k w r25 2.26k w r20 1.1 w c15 10nf c16 1f c31 1nf r8 2.37k w c8 82nf c9 8.2nf c17 220pf r19 220 w r23 1.5k w r24 1.2k w c22 4.7f tl431 r26 10k w moc 8102 c23 100nf r18 220 w t2 t1 l1: premier magnetics #tsd-734 l2: 33h, 10a dc t1: premier magnetics #tsd-736 t2: premier magnetics #tsd-735 premier magnetics: (714) 362-4211
ML4824 14 physical dimensions inches (millimeters) seating plane 0.240 - 0.260 (6.09 - 6.61) pin 1 id 0.295 - 0.325 (7.49 - 8.26) 0.740 - 0.760 (18.79 - 19.31) 0.016 - 0.022 (0.40 - 0.56) 0.100 bsc (2.54 bsc) 0.008 - 0.012 (0.20 - 0.31) 0.015 min (0.38 min) 16 0o - 15o 1 0.055 - 0.065 (1.40 - 1.65) 0.170 max (4.32 max) 0.125 min (3.18 min) 0.02 min (0.50 min) (4 places) package: p16 16-pin pdip
ML4824 15 physical dimensions inches (millimeters) seating plane 0.291 - 0.301 (7.39 - 7.65) pin 1 id 0.398 - 0.412 (10.11 - 10.47) 0.400 - 0.414 (10.16 - 10.52) 0.012 - 0.020 (0.30 - 0.51) 0.050 bsc (1.27 bsc) 0.022 - 0.042 (0.56 - 1.07) 0.095 - 0.107 (2.41 - 2.72) 0.005 - 0.013 (0.13 - 0.33) 0.090 - 0.094 (2.28 - 2.39) 16 0.009 - 0.013 (0.22 - 0.33) 0o - 8o 1 0.024 - 0.034 (0.61 - 0.86) (4 places) package: s16w 16-pin wide soic
ML4824 16 ? micro linear 1998. is a registered trademark of micro linear corporation. all other trademarks are the property of their respective owners. products described herein may be covered by one or more of the following u.s. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,8 62; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798. japan: 2,598,946; 2,619,299; 2,704,176. other patents are pending. micro linear reserves the right to make changes to any product herein to improve reliability, function or design. micro linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. the circuits contained in this data sheet are offered as possible applications only. micro linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. the customer is urged to consult with appropriate legal counsel before deciding on a particular application. ds 4 82 4- 01 2092 concourse drive san jose, ca 95131 tel: (408) 433-5200 fax: (408) 432-0295 www.microlinear.com part number pwm frequency temperature range package ML4824cp-1 1 x pfc 0c to 70c 16-pin pdip (p16) ML4824cp-2 2 x pfc 0c to 70c 16-pin pdip (p16) ML4824cs-1 1 x pfc 0c to 70c 16-pin wide soic (s16w) ML4824cs-2 2 x pfc 0c to 70c 16-pin wide soic (s16w) ML4824ip- 1 1 x p f c C40c to 85 c 16-pin pdip (p16) ML4824ip- 2 2 x p f c C40c to 85 c 16-pin pdip (p16) ( o bs ole te ) ML4824is-1 1 x pfc C40c to 85c 16-pin wide soic (s16w) ML4824is- 2 2 x p f c C40c to 85 c 16-pin wide soic (s16w) ( ob so let e) ordering information

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